Introduction to the min_9bit Module
In digital arithmetic and logic operations, especially within small-scale Arithmetic Logic Units (ALUs), modules that perform basic comparison functions are essential. The min_9bit module is one such component, designed to determine the minimum of two 9-bit signed numbers. This module plays a crucial role in the functionality of the 9-bit ALU, contributing to its ability to perform a range of arithmetic operations efficiently.
Functionality and Design
The min_9bit module operates on two 9-bit inputs, inputA and inputB, and outputs the smaller of the two numbers. The logic implemented in this module is as follows:
Sign Comparison:
The module first checks if inputA and inputB have the same sign (both positive or both negative) by comparing their most significant bits (MSBs), which represent the sign.
Determining the Minimum:
If both numbers have the same sign, the module compares their absolute values (ignoring the sign bit) to determine the smaller number.
If the numbers have different signs, the module selects the negative number as the minimum, assuming the standard representation where the MSB of 1 indicates a negative number.
Output Generation:
The result of this comparison logic is assigned to the output out, representing the minimum of the two inputs.
System Verilog implementation:
Testbench: